The present invention relates to field effect transistors and to integrated circuits.
For numerous applications, it would be desirable to be able to fabricate good quality field effect transistors in polycrystalline semiconductor material. Such a capability would lead to breakthroughs in at least two areas. First, silicon on insulator structures could be fabricated on a very wide variety of substrates. At present, silicon on insulator structures can only be used in those cases where a good lattice match between the silicon active device layer and the insulating substrate can be found. Secondly, and perhaps of even more importance, the capability for good quality polysilicon devices permits vertical integration. That is, at present integrated circuits are essentially two-dimensional devices, and active devices cannot be overlaid one on top of another. However, if it were possible to fabricate active devices having polysilicon channels, such active devices could be formed on an insulator layer on too of another active device. This opens the door to a whole new generation of integrated circuit device design.
However, the numerous prior attempts in the art to build transistors in polysilicon have encountered three major difficulties. First, the mobility (and hence the bulk conductivity) of polysilicon material is inherently very low. Second, leakage problems have normally been found with polysilicon transistors. Third, the threshold voltages of such transistors have been extremely large.
These problems are in some respects complementary. That is, by making the channel of a polysilicon transistor very long, the leakage current can be somewhat reduced. However, in this case, the low mobility of the polysilicon means that the device will have a very large series resistance, so that a huge low-gain device is likely to result if one attempts to design a practical polysilicon transistor using methods of the prior art.
Prior art attempts to design a good polysilicon transistor have typically used relatively thick polysilicon (e.g. 3500-7500 Angstroms) at modest doping channel levels of, e.g., 10.sup.16 or less per cubic centimeters, operated in the inversion mode. (I.e., the channel is n-type poly for a PMOS transistor having p+poly sources and drains.) Inversion mode is typically used to reduce leakage current. However, the result of such a device configuration is a very high threshold voltage, typically in the range of eight to ten volts. This is too high for most integrated circuit applications.
The present invention avoids these difficulties, by providing a field effect transistor having a channel region which is a thin (preferably 1000 to 1500 Angstroms) highly doped (preferably 10.sup.17 to 10.sup.18 per cc) polysilicon layer. The channel region is preferably hydrogen annealed, to reduce leakage current. Such a transistor is preferably operated in the accumulation mode. (I.e. the channel is p-type polysilicon for a PMOS device.) The combination of these characteristics results in a transistor which has low leakage current, high source/drain breakdown voltage, low threshold voltage, and low channel series resistance.
Thus, it is an object of the present invention to provide a polysilicon-channel transistor having low leakage.
It is a further object of the present invention to provide a polysilicon-channel transistor having low series resistance.
It is a further object of the present invention to provide a polysilicon-channel transistor having low series resistance and relatively small physical size.
It is a further object of the present invention to provide a field effect transistor having a channel region comprised of polycrystalline material, which has low leakage current.
It is a further object of the present invention to provide a field effect transistor having a channel composed of polycrystalline material, which has low on-state series resistance.
It is a further object of the present invention to provide a polysilicon field effect transistor having a low threshold voltage.
According to the present invention there is provided:
A field effect transistor comprising:
A channel region comprising polycrystalline semiconductor material;
Source and drain regions connected to said channel region; and
A gate positioned to apply an electric field to said channel region between said source and drain regions;
Wherein said channel has an equilibrium carrier concentration of at least five times 10.sup.16 per cubic centimeter.